TSMC A16 process targets Q4 mass production with 10% speed gain

TSMC has finished development of its 1.6nm-class A16 process, the industry's first angstrom node with backside power delivery, and plans Q4 mass production to lock in AI orders before rivals catch up.

Liu Pei-chen, a researcher at the Taiwan Institute of Economic Research, said the industry is shifting from a winner-takes-all structure toward specialization, with TSMC handling the most advanced miniaturized processes while others share back-end and packaging work.

Compared with N2P, TSMC's enhanced 2nm process, A16 delivers 8 percent to 10 percent higher speed at the same power, cuts power use 15 percent to 20 percent at the same speed, and raises transistor density 8 percent to 10 percent. The node uses vertical backside contacts to route power directly to transistor source and drain regions, freeing front-side space for signal wiring.

TSMC holds more than 70 percent of the global foundry market, versus Samsung's roughly 7 percent in the first quarter. The board on Aug. 11 approved $29.44 billion in capital spending for advanced processes and packaging, a bet that A16 will extend its lead into the angstrom era.

Backside power delivery breaks the wiring bottleneck

As process nodes shrink below 2nm, front-side chips must carry both power and signal interconnects, and the limited routing space creates congestion and voltage-drop problems. Backside power delivery moves the power network to the back of the wafer, freeing front-side space for signals while lowering resistance. TSMC's A16 uses dedicated vertical backside contacts to connect power directly to each transistor's source and drain, separating the power and signal networks.

The key differentiator is design compatibility. A16 preserves the gate density and NanoFlex design flexibility of N2P, keeping front-side structural changes to a minimum. That means customers already designing on TSMC's advanced nodes can migrate to A16 without rebuilding standard cells or design architectures — an advantage for AI accelerators and high-performance computing chips, where design cycles are long and IP complexity is high.

Rivals trail on mass-production timing

Samsung is prioritizing its SF2 2nm process and has secured long-term orders from Tesla, but it recently pushed its SF1.4 (1.4nm-class) node from 2027 to 2029 to focus on improving 2nm yields. Intel is advancing Intel 18A (about 1.8nm) and its 18A-P upgrade, with the next-generation Intel 14A (1.4nm) planned for risk production in the second half of 2027 and mass production in 2028 — nominally ahead of A16 but roughly two years later in volume output.

Intel's PowerVia backside power delivery required cell architecture changes during testing, and Samsung's SF2 approach may follow a similar path, according to industry sources. TSMC's A16, by contrast, integrates backside power while maintaining existing design compatibility, reducing customers' migration costs and time-to-market.

If A16 ramps on schedule, TSMC could secure a batch of high-end AI and HPC orders before Samsung and Intel scale their next-generation nodes. Advanced processes are a growing pillar of TSMC's revenue, and higher unit prices on N2, N2P, and A16 are expected to lift the AI contribution and reinforce its dominant foundry share. TSMC's ADR (TSM) trades as the primary beneficiary, while Samsung and Intel face the risk of ceding the high end of the market. Demand for AI chips has also tightened TSMC's CoWoS advanced packaging capacity, with some packaging volumes reportedly transferred to Intel's Malaysia plant — a sign the supply chain is dividing labor between leading-edge process work and back-end assembly.

This article is for informational purposes only and does not constitute investment advice.