Nvidia, Ambarella and an unnamed third partner are among the first customers for a signoff-ready 2nm chip design platform from Cadence and Samsung Foundry.
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3 companies tap Cadence-Samsung 2nm platform for AI chip designs
Cadence Design Systems and Samsung Foundry have certified a full portfolio of memory and interface IP on Samsung's second-generation 2nm process, creating a signoff-ready platform for AI infrastructure and physical AI chips across data center, edge and intelligent devices.
"AI infrastructure and physical AI are pushing the industry into advanced node and 3D-IC designs that demand far more capacity, integration and signoff confidence than ever before," Boyd Phelps, senior vice president and general manager of the Silicon Solutions Group at Cadence, said.
The multi-year agreement expands Cadence's IP portfolio to include Nvidia NVLink-C2C-enabled interconnect and CUDA-X GPU-accelerated libraries spanning high-speed SerDes, PCIe, UCIe and all leading memory interfaces on the second-generation 2nm node. Cadence's agentic AI digital, custom, 3D-IC and system design and analysis flows — including the Innovus Implementation System, Virtuoso Studio and Integrity 3D-IC Platform — are now certified for the node, supporting Samsung's 3D Cube-H design with hybrid copper bonding technology.
The collaboration comes as TSMC has booked every 2nm wafer through 2026 across five fabs running at full capacity, highlighting the insatiable demand for advanced-node manufacturing. Samsung's second-generation 2nm process gives chip designers an alternative foundry partner at a time when AI chip supply is the primary bottleneck for hyperscaler expansion plans.
Nvidia and Ambarella Lead the Customer Roster
Nvidia is leveraging the platform to deliver high-bandwidth interconnect through NVLink-C2C and CUDA-X GPU accelerated capabilities, foundational technologies for next-generation accelerated computing systems. Timothy Costa, vice president and general manager of computational engineering at Nvidia, said the GPU-accelerated design flows on Samsung's 2nm platform are "optimizing the performance and delivery of next-generation AI architectures and high-bandwidth interconnects."
Ambarella is developing its next-generation 2nm edge AI platform for robotics, drones, autonomous machines and advanced sensing applications. The company is using Cadence's PCIe 5.0 IP on the Samsung node. Chan Lee, chief operating officer at Ambarella, said having a "signoff-ready, co-optimized IP and tools solution, together with a robust, production-proven design kit and PDK" enables the company to reduce risk and accelerate innovation in low-power AI perception and physical AI computing.
Physical AI Opens a New Front in the Foundry War
Samsung is expanding its foundry push into physical AI semiconductors through a chiplet platform developed with Cadence, targeting chips for robotics, automotive systems, drones and industrial automation. The second-generation 2nm node enables key design features including glitch power optimization in the place-and-route flow and a smart hierarchical flow to achieve optimal performance, power and area.
The expanded certification also covers Samsung's 3D Cube-H design with a full system planning, implementation and signoff flow for hybrid copper bonding technology, including Cadence Cerebrus Intelligent Chip Explorer and the Integrity 3D-IC Platform. The platform includes silicon interposer auto-routing and optimization, ensuring tighter connectivity between analysis, signoff and verification.
Cadence and Samsung Foundry will highlight the enhanced partnership during the Samsung Advanced Foundry Ecosystem 2026 event, featuring technical sessions and demonstrations showcasing second-generation 2nm and 3D-IC design flows for GPU-accelerated AI workloads.
For investors, the deepened collaboration strengthens Cadence's competitive moat in the semiconductor design ecosystem. Cadence shares have benefited from the AI infrastructure buildout as chip designers race to tape out increasingly complex designs on advanced nodes. The partnership also signals that Samsung is serious about competing with TSMC for AI chip manufacturing, a market that could be worth tens of billions of dollars annually as hyperscalers and AI companies fight for capacity.
This article is for informational purposes only and does not constitute investment advice.
[1] Cadence and Samsung Foundry Deepen 2nm and 3D‑IC Collaboration to Meet Surging AI Infrastructure and Physical AI Demand[2] Samsung foundry targets robotics, auto AI chips with Cadence platform[3] TSMC just booked every 2nm wafer through 2026 — five fabs now running flat-out as AI customers reserve years of output before a single chip ships[4] 5 takeaways from Samsung Foundry’s design tie-up with Synopsys
