TSMC delays advanced CoPoS packaging to Q4 2030

Taiwan Semiconductor Manufacturing Co. has pushed the mass production of its next-generation CoPoS packaging technology to the fourth quarter of 2030, a roughly two-year delay that extends the strategic importance of its current CoWoS platform and reshapes investment logic across the semiconductor supply chain.

"The first CoPoS-packaged products are now expected by the end of 2030, compared to a prior market expectation for 2028," according to a DigiTimes report on Friday which cited sources within the supply chain.

The updated timeline indicates TSMC will begin R&D equipment installation in the third quarter of 2026, with pilot line orders following a year later. In contrast, capacity for the current CoWoS (Chip-on-Wafer-on-Substrate) technology is already fully booked for the next two years by major clients including Nvidia and AMD.

The postponement dims the outlook for equipment and material suppliers who were betting on an earlier CoPoS ramp-up, while providing a significant revenue tailwind for established partners in the CoWoS and SoIC supply chains. The shift solidifies TSMC's reliance on current-generation packaging for the medium term, impacting the performance scaling roadmap for future AI accelerators.

CoWoS and SoIC Expansion Fills the Gap

With CoPoS further on the horizon, TSMC is accelerating the expansion of its existing advanced packaging solutions. Demand from Nvidia, AMD, and various ASIC clients has completely reserved the company's CoWoS capacity for the next two years.

In parallel, TSMC plans a major expansion of its SoIC (System-on-Integrated-Chips) capacity. The company aims to increase monthly output at its Chiayi plant from nearly 10,000 wafers today to 50,000 wafers by 2027. Nvidia is reportedly set to be the primary offtaker for this expanded capacity, with about 10 percent designated for co-packaged optics (CPO) applications. This move provides clear, long-term order visibility for hybrid bonding equipment suppliers.

Technical Hurdles Push CoPoS Timeline

The delay primarily stems from fundamental technical challenges in the CoPoS (Compact Package on Substrate) architecture, specifically related to achieving "uniformity" and controlling "warpage" across the package. According to the DigiTimes report, TSMC has set an extremely high bar for its development partners.

The company is reportedly requiring some equipment suppliers to sign restrictive agreements, preventing them from selling related tools or technology to other clients. These stringent requirements increase the development costs and complexity for the entire supply chain, contributing to the extended timeline.

Supply Chain Readjusts to New Reality

The changing roadmap has ripple effects beyond TSMC's direct suppliers. A competing packaging plan known as CoWoP, reportedly led by Nvidia and partner SPIL, is now facing potential delays. The technical difficulty and high cost of this alternative have apparently dampened enthusiasm among participants.

With CoPoS production now a distant goal and CoWoP's future uncertain, the market's focus has intensified on TSMC's CoWoS and SoIC roadmaps. These two technologies will remain the core pillars of TSMC's advanced packaging strategy for the foreseeable future, forcing a re-evaluation of capital spending and order structures throughout the supply chain.

This article is for informational purposes only and does not constitute investment advice.